The invention relates generally to digital signal processing, and more particularly, to run-time configurable digital signal processors.
The explosive growth in telecommunication and multimedia applications demands flexible, efficient, high performance digital signal processing (DSP) devices. Current digital signal processors have many limitations when used for signal processing in telecommunication applications.
First, both general purpose DSPs and application specific DSPs have to deal with limited memory bandwidth. Second, in terms of performance, instruction based programmable DSPs typically lag ASICs by 1 to 2 orders of magnitude. This is a significant gap, especially for increasing demand from multimedia applications for wireless and wire line media. On the other hand, fixed logic based ASICs are not suitable for configurable signal processing, in addition to the reliance on external memory, which is also bandwidth limited.
The invention provides an architecture for digital signal processors that is based on embedded RAM (eRAM) technology. The invention exploits the very wide memory bandwidth available in eRAM, and the high memory density to achieve very high performance in signal processing functions such as filtering, scaling, and other arithmetic operations. Multiplication-free digital signal processing is made possible by replacing multiplication with memory based shift and add operations. As another advantage, the DSP according to the invention is run-time reconfigurable. This enables configurable signal receivers such as software defined radio and television receivers, or software based wireless telephones. Because the majority of the signal processing functions are memory-based, the DSP according to the invention is ideal for implementing scalable signal processors.
More particularly, the invention provides an apparatus that receives and demodulates digital signals encoded in multiple formats. The apparatus includes multiple processor units and a memory embedded with the processor units, and a cache connected to each of the processor units. The cache communicates between the plurality of processors. The embedded memory can include data and instruction memory. The processor units and memory are configured as a multi-mode receiver demodulator front-end capable of receiving digitally modulated signals in multiple formats, and demodulating the signals in real-time in response any one of the multiple formats.